During data conversion by an analog-to-digital converter, analog signals must first be sampled and then converted to a digital value. A conventional technique for this utilizes a SAR data conversion algorithm. One architecture of this conversion algorithm uses a plurality of switched capacitors that are selectively switched in to test each bit. There will be one switched capacitor for each bit ranking from the most significant bit (MSB) to the least significant bit (LSB). During a conversion cycle on a 12-bit resolution SAR converter, in one example, there will be at least be twelve tests performed. As each bit is tested, that bit is set to a “1” or a “0” during the conversion cycle at the end of the test for that bit. This 12-bit value (for a 12-bit SAR data converter in the present example) is output to a register as the result of the data conversion operation. The total conversion time from the beginning of the MSB test to the end of the LSB test is termed the “conversion cycle.” It should be understood that other types of data converters can also be used for the data conversion operation.
Since the throughput of a conventional SAR data converter is defined as the sample time (track time) plus the number of clock cycles of a data conversion clock required to perform tests on each bit, then a complete conversion cycle will have the time thereof defined by the number of bits associated with data converter and the speed of the SAR data converter clock. The speed of the SAR data converter is, of course, a function of the fastest clock that is present on an integrated circuit containing the data converter. This clock can be significantly faster than the sampling rate of the analog input data. For example, there may be a sampling frequency wherein the data is sampled followed by the initiation of a conversion cycle. However, at the end of the conversion cycle, there may be a considerable amount of time until the next sample is taken. As the clock frequency decreases, the amount of time between the end of a conversion cycle and the beginning of the next conversion cycle increases. This is important for systems that are required to sample multiple analog inputs and convert each of these analog inputs to store the digital value, and still leave time for other processing. One such integrated circuit that performs such operations is a C8051F410, manufactured by the present assignee. In some situations, the purpose for measuring the analog input voltage is to compare that analog input voltage with a fixed threshold and, when the analog input voltage is above the threshold in one situation, below the threshold in another situation or within/outside the window of two thresholds, a digital comparator can be utilized, which will have the output thereof raised high to possibly provide an interrupt to a processor. In some situation, the processor is placed into a sleep mode with a low power consumption wherein the processor is “awakened” is response the generation of the interrupt-to jump to a higher clock speed and process data. One situation that this can be utilized in is that associated with a temperature sensor wherein the temperature rises above a predetermined level and the processor is awakened to take some action. Even though the decision could be made with just the testing of one or two of the MSBs, the entire conversion cycle must be processed, which constitutes wasted clock cycles. However, the amount of time to sample the process each sampled analog input through the entire conversion cycle can consume a significant amount of time as the need for faster and faster processing of the analog inputs increases and, thus, these wasted clock cycles become more important.